The present invention relates to a video graphic control method and controller for sending graphic data from a processing device to a display device.
A conventional video graphic controller used to display video graphic data on a display device such as a liquid crystal device (LCD) in response to an instruction from a central processing unit (CPU) such as a personal computer (PC) is described with reference to FIG. 4 of the figures identified hereinafter.
A video graphic controller 2 is located between a central processing unit 4 and a frame memory 18 acting as a video storage element in order to control video data. The CPU 4 is connected to a bus interface unit 6 in the video graphic controller 2. The bus interface unit 6 outputs to a memory interface unit 12 video data from the CPU 4, and outputs to a graphic engine 8 drawing information data from the CPU 4.
The graphic engine 8 generates video data from received drawing information data, and outputs the video data to the memory interface unit 12. The memory interface unit 12 reads, writes, and stores video data from, to, and in a specified address of the frame memory 18.
The frame memory 18 can store, for example, 1 megabytes (MB) of video data, and the video data in the pixels on the screen of the display device which are arranged from the upper left of the screen down to the lower right thereof is input to the frame memory 18 in the order of storage addresses. The frame memory 18 is connected to a latch 14 in the memory interface unit 12 via a 32-bit data bus, and outputs 4 pixels (32 bits) of video data at a time to the latch 14.
Four pixels of video data latched by the latch 14 are stored sequentially in a display FIFO 16, and output sequentially to a display device 30 as 1 pixel (8 bits) of video data in a first-in-first-out manner.
Graphic performance under such a conventional video graphic controller relates directly to the amount of the memory bandwidth (the transfer rate) available to a graphic engine. The amount of the memory bandwidth used by the graphic engine and CPU depends upon the resolution of a screen, range of gradation, and refresh rate of the screen.
The following methods may be used to substantially increase the memory bandwidth available to the graphic engine in order to improve graphic performance:
1. Use a high-speed memory (DRAM); PA1 2. Use a dual port memory (VRAM); or PA1 3. Increase the number of memory data buses. PA1 1. The use of the faster DRAM provides a memory band width 1.4 times that of the DRAM having a normal transfer rate. The band width available to the graphic engine thus doubles, but manufacturing costs increase 1.5 times to twice instead. PA1 2. The use of the VRAM that is a dual port memory enables the band width for the engine to increase about 2.5 times, but manufacturing costs double instead. PA1 3. If the number of memory data buses is increased to form a DRAM with a data width of 64 bits, a transfer rate twice that of a 32-bit DRAM can be obtained. The band width for the graphic engine thus increases 3.5 times, but manufacturing costs also double.
Although these three methods serve to improve graphic performance, they have respective problems. These problems are described using Table 1 that compares conventional 32-bit frame buffer bandwidths.
TABLE 1 ______________________________________ 32-bit 32-bit DRAM 32-bit 64-bit Memory configuration DRAM (High Speed) VRAM DRAM ______________________________________ Memory band width (MB/s) 100 140 100 200 Display band width (MB/s) 60 60 60 60 (1024 .times. 768 .times. 8 .times. 70 Hz) Memory band width avail- 40 80 100 140 able to graphic engine (MB/s) (1024 .times. 768 .times. 8 .times. 70 Hz) Cost 1.0 1.5-2.0 2.0 2.0 ______________________________________
The storage amount of a storage element for video display is usually about 1 megabyte (MB), and two 256K.times.16-bit DRAMs are used to form a DRAM with a data width of 32 bits. A DRAM with a data width of 32 bits has a memory band width (write/read rate: MB/s) of about 100 MB/s. The amount of display data required for display on an LCD or CRT (the display band width: MB/s), however, is 60 MB/s for a display device that has a display area of 1,024.times.768 pixels, that displays 8-bit, that is, 256-color gradation, and that has a refresh rate of 70 Hz.
The video data transfer amount that can be assigned for the high-speed updating of the screen by the graphic engine (the graphic engine/CPU band width: MB/s) is thus 40 MB/s.
Table 1 indicates the following matters:
All these methods tend to increase power consumption, and cannot be adopted now due to demands for reduced manufacturing costs and power consumption.